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MOSEL VITELIC
V29C51400T/V29C51400B 4 MEGABIT (262,144 x 16 BIT/524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
Description
PRELIMINARY
Features
s s s s s s 256K x 16-bit or 512K x 8-bit Organization Address Access Time: 70, 90, 120 ns Single 5V 10% Power Supply Sector Erase Mode Operation 16KB Boot Block (lockable) 1K bytes per Sector, 512 Sectors - Sector-Erase Cycle Time: 10ms (Max) - Byte-Write Cycle Time: 20s (Max) Minimum 10,000 Erase-Program Cycles Low power dissipation - Active Read Current: 19mA (Typ) - Active Program Current: 30mA (Typ) - Standby Current: 100A (Max) Hardware Data Protection Low VCC Program Inhibit Below 3.5V Self-timed write/erase operations with end-ofcycle detection - DATA Polling - Toggle Bit CMOS and TTL Interface Available in two versions - V29C51400T (Top Boot Block) - V29C51400B (Bottom Boot Block) Packages: - 48-pin TSOP
s s
s s s
s s
s
The V29C51400T/V29C51400B is a high speed 262,144 x 16 bit or 524,288 x 8-bit CMOS flash memory. Writing or erasing the device is done with a single 5 Volt power supply. The device has separate chip enable CE, write enable WE, and output enable OE controls to eliminate bus contention. The V29C51400T/V29C51400B offers a combination of: Boot Block with Sector Erase/Write Mode. The end of write/erase cycle is detected by DATA Polling of I/O7 or by the Toggle Bit I/O6. The V29C51400T/V29C51400B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. The device also supports full chip erase. Boot block architecture enables the device to boot from a protected sector located either at the top (V29C51400T) or the bottom (V29C51400B). All inputs and outputs are CMOS and TTL compatible. The V29C51400T/V29C51400B is ideal for applications that require updatable code and data storage.
Device Usage Chart
Operating Temperature Range 0C to 70 C Package Outline T * 70 * Access Time (ns) 90 * 120 * Temperature Mark Blank
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
V29C51400T/V29C51400B
V
29
C
51 400
T
-
OPERATING VOLTAGE 51: 5V
DEVICE
SPEED
PKG.
TEMP. BLANK (0C TO 70C)
BOOT BLOCK LOCATION T: TOP B: BOTTOM
70: 70ns 90: 90ns 12: 120ns
T = TSOP
51400-01
Pin Configurations
Pin Names
A0-A17 I/O0-I/O14 Address Inputs Data Input/Output Data Input/Output, Word Mode (LSB Address Input, Byte Mode) Chip Enable Output Enable Write Enable 5V 10% Power Supply Ground No Connect Ready/Busy Output Selects 8-Bit or 16-Bit mode
A15 A14 A13 A12 A11 A10 A9 A8 N/C N/C WE N/C N/C N/C RY/BY N/C A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-Pin TSOP Standard Pinout Top View
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
51400-02
A16 BYTE GND I/O15(A-1) I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0
I/O15 (A-1)
CE OE WE VCC GND NC RY/BY BYTE
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
Functional Block Diagram
V29C51400T/V29C51400B
X-Decoder
4,194,304 Bit Memory Cell Array
A0-A17
Address buffer & latches
Y-Decoder
RY/BY CE OE WE BYTE
Control Logic
I/O Buffer & Data Latches
I/O0-I/O15 (A-1)
51400-03
Capacitance (1,2)
Symbol
CIN COUT CIN2
Parameter
Input Capacitance Output Capacitance Control Pin Capacitance
Test Setup
VIN = 0 VOUT = 0 VIN = 0
Typ.
6 8 8
Max.
8 12 10
Units
pF pF pF
NOTE: 1. Capacitance is sampled and not 100% tested. 2. TA = 25C, VCC = 5V 10%, f = 1 MHz.
Latch Up Characteristics(1)
Parameter
Input Voltage with Respect to GND on A9, OE Input Voltage with Respect to GND on I/O, address or control pins VCC Current NOTE: 1. Includes all pins except VCC. Test conditions: VCC = 5V, one pin at a time.
Min.
-1 -1 -100
Max.
+13 VCC + 1 +100
Unit
V V mA
AC Test Load
+5.0 V IN3064 or Equivalent Device Under Test IN3064 or Equivalent CL = 100 pF 6.2 k IN3064 or Equivalent IN3064 or Equivalent
51400-04
2.7 k
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
Absolute Maximum Ratings(1)
Symbol
VIN VIN VCC TSTG TOPR IOUT
V29C51400T/V29C51400B
Parameter
Input Voltage (input or I/O pins) Input Voltage (A9 pin, OE) Power Supply Voltage Storage Temperature (Plastic) Operating Temperature Short Circuit Current(2)
Commercial
-2 to +7 -2 to +13 -0.5 to +5.5 -65 to +125 0 to +70 200 (Max.)
Unit
V V V C C mA
NOTE: 1. Stress greater than those listed unders "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. No more than one output maybe shorted at a time and not exceeding one second long.
DC Electrical Characteristics
(over the commercial operating range)
Parameter Name
VIL VIH IIL IOL VOL VOH ICC1
Parameter
Input LOW Voltage Input HIGH Voltage Input Leakage Current Output Leakage Current Output LOW Voltage Output HIGH Voltage Read Current
Test Conditions
VCC = VCC Min. VCC = VCC Max. VIN = GND to VCC, VCC = VCC Max. VOUT = GND to VCC, VCC = VCC Max. VCC = VCC Min., IOL = 2.1mA VCC = VCC Min, IOH = -400A CE = OE = VIL, WE = VIH, all I/Os open, Address input = VIL/VIH, at f = 1/tRC Min., VCC = VCC Max. CE = WE = VIL, OE = VIH, VCC = VCC Max. CE = OE = WE = VIH, VCC = VCC Max. CE = OE = WE = VCC - 0.3V, VCC = VCC Max. CE = OE = VIL, WE = VIH CE = OE = VIL, WE = VIH, A9 = VH Max.
Min.
-- 2 -- -- -- 2.4 --
Max.
0.8 -- 1 1 0.4 -- 40
Unit
V V A A V V mA
ICC2 ISB ISB1 VH IH
Write Current TTL Standby Current CMOS Standby Current Device ID Voltage for A9 Device ID Current for A9
-- -- -- 11.5 --
50 2 100 12.5 50
mA mA A V A
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
AC Electrical Characteristics
(over all temperature ranges) Read Cycle
Parameter Name
tRC tAA tACS tOE tCLZ tOLZ tDF tOH
V29C51400T/V29C51400B
-70 Parameter
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time CE Low to Output Active OE Low to Output Active OE or CE High to Output in High Z Output Hold from Address Change
-90 Min.
90 -- -- -- 0 0 0 0
-12 Min.
120 -- -- -- 0 0 0 0
Min.
70 -- -- -- 0 0 0 0
Max.
-- 70 70 35 -- -- 20 --
Max.
-- 90 90 45 -- -- 20 --
Max.
-- 120 120 60 -- -- 30 --
Unit
ns ns ns ns ns ns ns ns
Program (Erase/Program) Cycle
Parameter Name Parameter
tWC tAS tAH tCS tCH tOES tOEH tWP tWPH tDS tDH tWHWH1 tWHWH2 tWHWH3 Write Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time OE Setup Time OE High Hold Time WE Pulse Width WE Pulse Width High Data Setup Time Data Hold Time Programming Cycle Sector Erase Cycle Chip Erase Cycle
-70 Min.
70 0 45 0 0 0 0 35 20 30 0 -- -- --
-90 Max.
-- -- -- -- -- -- -- -- -- -- -- 20 10 --
-12 Max.
-- -- -- -- -- -- -- -- -- -- -- 20 10 --
Typ.
-- -- -- -- -- -- -- -- -- -- -- -- -- 2
Min.
90 0 45 0 0 0 0 45 30 30 0 -- -- --
Typ.
-- -- -- -- -- -- -- -- -- -- -- -- -- 2
Min.
120 0 50 0 0 0 0 50 35 30 0 -- -- --
Typ.
-- -- -- -- -- -- -- -- -- -- -- -- -- 2
Max.
-- -- -- -- -- -- -- -- -- -- -- 20 10 --
Unit
ns ns ns ns ns ns ns ns ns ns ns s ms sec
Word/Byte Configuration
Parameter Name Parameter
tELFL/tELFH tFLQZ tFHQV CE to BYTE Switching Low/High BYTE Low to Output in HIGH BYTE High to Output Active
-70 Min.
-- -- 70
-90 Typ. Max. Min.
-- -- -- 5 20 -- -- -- 120
-12 Typ. Max. Unit
-- -- -- 5 30 -- ns ns ns
Typ. Max. Min.
-- -- -- 5 20 -- -- -- 90
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
BYTE Timings for Read Operations
CE
V29C51400T/V29C51400B
OE
BYTE
tELFL BYTE Switching from word to byte mode I/O0--I/O14 Data Output (I/O0--I/O14) Data Output (I/O0--I/O7)
I/O15(A-1)
I/O15 Output tFLQZ tELFH
Address Input
BYTE BYTE Switching from byte to word mode
I/O0--I/O14
Data Output (I/O0--I/O7) Address Input tFHQV
Data Output (I/O0--I/O14) I/O15 Output
I/O15(A-1)
BYTE Timings for Write Operations
CE The falling edge of the last WE signal WE BYTE tAS t AH
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
Waveforms of Read Cycle
tRC ADDRESS tAA CE tCE tOE OE tOLZ WE tCLZ I/O HIGH-Z tOH VALID DATA OUT tAA RY/BY
V29C51400T/V29C51400B
tDF
VALID DATA OUT
HIGH-Z
51400-05
Waveforms of WE Controlled-Program Cycle
3rd bus cycle tWC tAS ADDRESS 5555H tCH CE PA tAH PA(2) tRC
OE tOES WE tCS tWPH tDS tDH I/O A0H PD(3) I/O7(1) DOUT tOH
51400-06
tWP
tWHWH1
tDF tOE
NOTES: 1. I/O7: The output is the complement of the data written to the device. 2. PA: The address of the memory location to be programmed. 3. PD: The data at the byte address to be programmed.
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
Waveforms of CE Controlled-Program Cycle
tWC ADDRESS 5555H PA tAS tAH WE PA(1)
V29C51400T/V29C51400B
tRC
OE tWP CE tOES tWPH tDS tDH I/O A0H PD(2) I/O7 DOUT tOH
51400-07
tWHWH1
tDF tOE
Waveforms of Erase Cycle(1)
tWC ADDRESS 5555H tAS 2AAAH 5555H tAH CE 5555H 2AAAH (5555H for Chip Erase) SA
OE tWP WE tCS tDS tDH I/O AAH 55H 80H AAH 55H tWPH tWHWH 2
3
(10H for Chip Erase) 30H
51400-08
NOTES: 1. PA: The address of the memory location to be programmed. 2. PD: The data at the byte address to be programmed. 3. SA: The sector address for Sector Erase.
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
Waveforms of DATA Polling Cycle
tCH CE tOE OE tOEH WE tCE tWHWH1 (2 or 3) I/O7 I/O7 I/O7
V29C51400T/V29C51400B
tDF
tOH HIGH-Z
VALID DATA OUT
I/O0-I/O6
I/O0-I/O6
INVALID
VALID DATA OUT
HIGH-Z
51400-09
Waveforms of Toggle Bit Cycle
CE tOEH WE
OE
I/O6 stop toggling tWHWH1 (2 or 3)
51400-10
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
V29C51400T/V29C51400B
V29C51400Tx8 16KB Boot Block 7FFFFH 7C000H
V29C51400Bx8
V29C51400Tx16 16KB Boot Block 3FFFFH 3E000H
V29C51400Bx16
00000H
00000H
3FFFH 16KB Boot Block 00000H
00000H
00000H
1FFFH 16KB Boot Block 00000H
51400-11
16KB Boot Block = 32 Sectors BYTE MODE
16KB Boot Block = 32 Sectors WORD MODE
World/Byte Configuration
The BYTE pin controls whether the device data I/O pins I/O0-I/O15 operate in the byte or word configuration. If the BYTE pin is set at logic '1', the device is in word configuration, I/O0-I/O15 are active and controlled by CE and OE. If BYTE pin is set at logic '0', the device is in byte configuration, and only data I/O pins I/O0-I/O7 are active and controlled by CE and OE. The data I/O pins I/O8-I/O14 are tri-stated, and the I/O15 pin is used as an input for the LSB (A-1) address function.
Output Disable
Returning OE or CE HIGH, whichever occurs first will terminate the read operation and place the l/O pins in the HIGH-Z state.
Standby
The device will enter standby mode when the CE signal is HIGH. The l/O pins are placed in the HIGH-Z, independent of the OE input state.
Command Sequence
The V29C51400T/V29C51400B does not provide the "reset" feature to return the chip to its normal state when an incomplete command sequence or an interruption has happened. In this case, normal operation (Read Mode) can be restored by issuing a "non-existent" command sequence, for example Address: 5555H, Data FFH.
Functional Description
The V29C51400T/V29C51400B consists of 512 equally-sized sectors of 512 bytes each. The 16 KB lockable Boot Block is intended for storage of the system BIOS boot code. The boot code is the first piece of code executed each time the system is powered on or rebooted. The V29C51400 is available in two versions: the V29C51400T with the Boot Block address starting from 7C000H to 7FFFFH, and the V29C51400B with the Boot Block address starting from 00000H to 3FFFH.
Byte Write Cycle
The V29C51400T/V29C51400B is programmed on a byte-by-byte basis. The byte write operation is initiated by using a specific four-bus-cycle sequence: two unlock program cycles, a program setup command and program data program cycles (see Table 2). During the byte write cycle, addresses are latched on the falling edge of either CE or WE, whichever is last. Data is latched on the rising edge of CE or WE, whichever is first. The byte write cycle can be CE controlled or WE controlled.
Read Cycle
A read cycle is performed by holding both CE and OE signals LOW. Data Out becomes valid only when these conditions are met. During a read cycle WE must be HIGH prior to CE and OE going LOW. WE must remain HIGH during the read operation for the read to complete (see Table 1).
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
Sector Erase Cycle
The V29C51400T/V29C51400B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. Sector erase operation is initiated by using a specific six-bus-cycle sequence: Two unlock program cycles, a setup command, two additional unlock program cycles, and the sector
V29C51400T/V29C51400B
erase command (see Table 2). A sector must be first erased before it can be re-written. While in the internal erase mode, the device ignores any program attempt into the device. The internal erase completion can be determined via DATA polling or toggle bit status. The V29C51400T/V29C51400B is shipped fully erased (all bits = 1).
Table 1. Operation Modes Decoding
Decoding Mode
Read Byte Write Standby Autoselect Device ID Autoselect Manufacture ID Enabling Boot Block Protection Lock Disabling Boot Block Protection Lock Output Disable
CE
VIL VIL VIH VIL VIL VIL VH VIL
OE
VIL VIH X VIL VIL VH VH VIH
WE
VIH VIL X VIH VIH VIL VIL VIH
A0
A0 A0 X VIH VIL X X X
A1
A1 A1 X VIL VIL X X X
A9
A9 A9 X VH VH VH VH X
I/O
READ PD HIGH-Z CODE CODE X X HIGH-Z
NOTES: 1. X = Don't Care, VIH = HIGH, VIL = LOW, VH = 12.5V Max. 2. PD: The data at the byte address to be programmed.
Table 2. Command Codes
Command Sequence Reset/Read Reset/Read Autoselect Mode Word Byte Word Byte Word/Byte Program Chip Erase Sector Erase Word Byte Word Byte Word Byte 6 0 4 5555H AAAAH 5555H AAAAH 5555H AAAAH AAH AAH AAH 2AAAH 5555H 2AAAH 5555H 2AAAH 5555H 55H 55H 55H 5555H AAAAH 5555H AAAAH 5555H AAAAH 80H 80H 5555H AAAAH 5555H AAAAH AAH AAH 2AAAH 5555H 2AAAH 5555H 55H 55H 5555H AAAAH SA 30H 10H A0H 3 Bus Write Cycles Req'd 1 3 First Bus Program Cycle Address Data XXXXH 5555H AAAAH 5555H AAAAH AAH F0H AAH 2AAAH 5555H 2AAAH 5555H 55H 55H 5555H AAAAH 5555H AAAAH 90H 01H
13H, B3H (B Device ID) 13H, B3H (B Device ID)
Second Bus Program Cycle Address Data
Third Bus Program Cycle Address Data F0H
Fourth Bus Program Cycle Address Data RA RD
Fifth Bus Program Cycle Address Data
Six Bus Program Cycle Address Data
00H
PA
40H (Manuf. ID)
PD(4)
NOTES: 1. RA: Read Address 2. RD: Read Data 3. PA: The address of the memory location to be programmed. 4. PD: The data at the byte address to be programmed. 5. SA(5): Sector Address
Chip Erase Cycle
The V29C51400T/V29C51400B features a chiperase operation. The chip erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup
command, two additional unlock program cycles, and the chip erase command (see Table 2). The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and terminates when the data on DQ7 is "1".
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
Program Cycle Status Detection
There are two methods for determining the state of the V29C51400T/V29C51400B during a program (erase/write) cycle: DATA Polling (I/O7) and Toggle Bit (I/O6).
V29C51400T/V29C51400B
status, device ID and manufacturer ID. Entering Autoselect mode is accomplished by applying a high voltage (VH) to the A9 Pin, or through a sequence of commands (as shown in table 2). Device will exit this mode once high voltage on A9 is removed or another command is loaded into the device.
DATA Polling (I/O7)
The V29C51400T/V29C51400B features DATA polling to indicate the end of a program cycle. When the device is in the program cycle, any attempt to read the device will received the complement of the loaded data on I/O7. Once the program cycle is completed, I/O7 will show true data, and the device is then ready for the next cycle.
Boot Block Protection Status
In Autoselect mode, performing a read at address location 7BXX2H (V29C51400T) or 0CXX2H (V29C51400B) will indicate boot block protection status. If the data is 01H, the boot block is protected. If the data is 00H, the boot block is unprotected. This is also shown is table 3.
Toggle Bit (I/O6)
The V29C51400T/V29C51400B also features another method for determining the end of a program cycle. When the device is in the program cycle, any attempt to read the device will result in l/O6 toggling between 1 and 0. Once the program is completed, the toggling will stop. The device is then ready for the next operation. Examining the toggle bit may begin at any time during a program cycle.
Device ID
In Autoselect mode, performing a read at address XXX1H will determine whether the device is a Top Boot Block device or a Bottom Boot Block device. If the data is 13H, the device is a Top Boot Block. If the data is B3H, the device is a Bottom Boot Block device (see Table 3).
Manufacturer ID
In Autoselect mode, performing a read at address XXXX0H will determine the manufacturer ID. 40H is the manufacturer code for Mosel Vitelic Flash.
Boot Block Protection Enabling/Disabling
The V29C51400T/V29C51400B features hardware Boot Block Protection. The boot block sector protection is enabled when high voltage (12.5V) is applied to OE and A9 pins with CE pin LOW and WE pin LOW. The sector protection is disabled when high voltage is applied to OE, CE and A9 pins with WE pin LOW. Other pins can be HIGH or LOW. This is shown in table 1.
Hardware Data Protection
VCC Detection: the program operation is inhibited when VCC is less than 3.5V. Noise Protection: a CE or WE pulse of less than 5ns will not initiate a program cycle. Program Inhibit: holding any one of OE LOW, CE HIGH or WE HIGH inhibits a program cycle.
Autoselect Mode
The V29C51400T/V29C51400B features an Autoselect mode to identify boot block locking
Table 3. Autoselect Decoding
Address Decoding Mode
Boot Block Protection
Boot Block
Top Bottom
A0
VIL VIL VIH
A1
VIH VIH VIL
A2-A13
X X X
A14-A17
VIH VIL X
Data I/O0-I/O7
01H: protected 00H: unprotected 13H B3H
Device ID
Top Bottom
Manufacture ID NOTE: 1. X = Don't Care, VIH = HIGH, VIL = LOW.
VIL
VIL
X
X
40H
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
Byte Program AlgorithmChip/Sector Erase Algorithm
V29C51400T/V29C51400B
Write Byte-Write Command Sequence
Write Erase Command Sequence
Add/Data 5555H/AAH
Add/Data 5555H/AAH
2AAAH/55H Four Bus Cycle Sequence 5555H/A0H
2AAAH/55H
5555H/80H Six Bus Cycle Sequence
PA/PD
5555H/AAH
Data Polling or Toggle bit successfully completed or tWTWH (2 or 3) timeout
2AAAH/55H
Writing Completed
5555H/10H (Chip Erase) SA/30H (Sector Erase)
Data Polling or Toggle bit successfully completed or tWTWH (2 or 3) timeout
Erase Completed
51400-12
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
DATA Polling Algorithm
Read I/O7 Address = PBA(1)
V29C51400T/V29C51400B
Toggle Bit Algorithm
Read I/O6
No
I/O7 = Data
Read I/O6
Yes Yes Program Done No I/O6 Toggle
Program Done
51400-13
NOTE: 1. PBA: The byte address to be programmed.
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
Package Diagrams
48-pin TSOP
Pin 1 I.D. 1 48
V29C51400T/V29C51400B
11.90 12.10 0.08 0.20 24 18.30 18.50 19.80 20.20 25 0.10 0.21
Detail "A"
0 5 0.50 0.70
1.20 MAX See Detail A 0.25MM (0.0098") BSC 0.05 0.15 0.50 BSC 0.95 1.05
V29C51400T/V29C51400B Rev. 1.5 October 2000
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MOSEL VITELIC
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888
V29C51400T/V29C51400B
UK & IRELAND
SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516
SINGAPORE
10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013
HONG KONG
19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 852-2666-3307 FAX: 852-2770-8011
JAPAN
ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402
GERMANY (CONTINENTAL EUROPE & ISRAEL)
BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
SOUTHWESTERN
302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807
CENTRAL, NORTHEASTERN & SOUTHEASTERN
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341
(c) Copyright 2000, MOSEL VITELIC Inc.
10/00 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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